Three-dimensional (3D) integrated circuits have proven to be the favored approach for improving the performance of semiconductor products. Density can be upgraded many fold by stacking chips or wafers. Significant speed improvement can also be expected because the interconnecting wires linking the chips are shortened substantially.
Aligning solder bumps and pads during the manufacturing process of 3D chip stacks is a cumbersome process. Misalignment of solder bumps diminishes the manufacturing yield and the signal integrity of the interconnections. Traditional alignment techniques include mechanical and/or optical alignment methods.